Direct Digital Frequency Synthesizer Design and Implementation on FPGA

Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA

This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...

design and simulation of a modified 32-bit rom-based direct digital frequency synthesizer on fpga

this paper presents a modified 32-bit rom-based direct digital frequency synthesizer (ddfs). maximum output frequency of the ddfs is limited by the structure of the accumulator used in the ddfs architecture. the hierarchical pipeline accumulator (hpa) presented in this paper has less propagation delay time rather than the conventional structures. therefore, it results in both higher maximum ope...

Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA

DDFS (Direct Digital Frequency Synthesizer) is a new technique of frequency synthesizes which introduces the advanced digital processing theory into frequency synthesis. A direct digital frequency synthesizer is composed of a phase accumulator, an adder, an ROM for wave pattern saving, a D/A converter and a LPF (low pass filter). With the rapid development of VLSI, the speed of algorithm is req...

Implementation of FPGA Architecture for OFDM-SDR with an optimized Direct Digital Frequency Synthesizer

A Software Defined Radio (SDR) is defined as a radio in which the receive digitization is performed at some stage downstream from the antenna, typically after wideband filtering, low noise amplification, and down conversion to a lower frequency in subsequent stages with a reverse process occurring for the transmit digitization. In an SDR, Digital Signal Processing in flexible and reconfigurable...

Implementing and Optimizing a Direct Digital Frequency Synthesizer (DDFS) on FPGA